PC912XDP512F0CFVR datasheet(378/1348 Pages) FREESCALE

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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

378

Freescale Semiconductor

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some

variation in between. If the channel is not enabled, then writes to the period register will go directly to the

latches as well as the buffer.

NOTE

Reads of this register return the most recent value written. Reads do not

necessarily return the value of the currently active period due to the double

buffering scheme.

See Section 8.4.2.3, “PWM Period and Duty” for more information.

To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,

or SB) and multiply it by the value in the period register for that channel:

•

Left aligned output (CAEx = 0)

•

PWMx Period = Channel Clock Period * PWMPERx Center Aligned Output (CAEx = 1)

PWMx Period = Channel Clock Period * (2 * PWMPERx)

For boundary case programming values, please refer to Section 8.4.2.8, “PWM Boundary Cases”.

Read: Anytime

Write: Anytime

8.3.2.14

PWM Channel Duty Registers (PWMDTYx)

There is a dedicated duty register for each channel. The value in this register determines the duty of the

associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value

a match occurs and the output changes state.

The duty registers for each channel are double buffered so that if they change while the channel is enabled,

the change will NOT take effect until one of the following occurs:

•

The effective period ends

•

The counter is written (counter resets to $00)

•

The channel is disabled

In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,

not some variation in between. If the channel is not enabled, then writes to the duty register will go directly

to the latches as well as the buffer.

76543210

Bit 7

Bit 0

Reset

11111111

Figure 8-15. PWM Channel Period Registers (PWMPERx)

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