PC912XDP512F0CFVR datasheet(151/1348 Pages) FREESCALE

151 / 1348 page

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

151

4.3.2.16

ATD Conversion Result Registers (ATDDRx)

The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the

result registers bases on two criteria. First there is left and right justiﬁcation; this selection is made using

the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using

the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left

justiﬁed format. Signed data selected for right justiﬁed format is ignored.

Read: Anytime

Write: Anytime in special mode, unimplemented in normal modes

4.3.2.16.1

Left Justiﬁed Result Data

76543210

R (10-BIT)

R (8-BIT)

BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

Reset

00000000

= Unimplemented or Reserved

Figure 4-18. Left Justiﬁed, ATD Conversion Result Register x, High Byte (ATDDRxH)

76543210

R (10-BIT)

R (8-BIT)

BIT 1

BIT 0

Reset

00000000

= Unimplemented or Reserved

u = Unaffected

Figure 4-19. Left Justiﬁed, ATD Conversion Result Register x, Low Byte (ATDDRxL)

PC912XDP512F0CFVR データシート(PDF) 151 Page - Freescale Semiconductor, Inc

PC912XDP512F0CFVR データシート(HTML) 151 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード