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LPC4350 データシート(PDF) 108 Page - NXP Semiconductors

部品番号 LPC4350
部品情報  32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet two High-speed USBs; advanced configurable peripherals
PDF  145 Pages
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC4350 データシート(HTML) 108 Page - NXP Semiconductors

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LPC4350_30_20_10
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 2.1 — 23 September 2011
108 of 145
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
11.6 SSP interface
[1]
Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2]
Tamb = 40 C to 85 C; VDD(REG)(3V3) = 2.0 V to 3.6 V; VDD(IO) = 2.0 V to 3.6 V.
[3]
Tcy(clk) = 12  Tcy(PCLK).
[4]
Tamb = 25 C; VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V.
Table 15.
Dynamic characteristics: SSP pins in SPI mode
Symbol
Parameter
Conditions
Min
Max
Unit
Tcy(PCLK)
PCLK cycle time
<tbd>
-
ns
Tcy(clk)
clock cycle time
full-duplex mode
[1]
<tbd>
-
ns
when only
transmitting
<tbd>
-
ns
SSP master
tDS
data set-up time
in SPI mode
[2]
<tbd>
Tcy(clk)
ns
tDH
data hold time
in SPI mode
[2]
-
<tbd>
ns
tv(Q)
data output valid time
in SPI mode
[2]
-
<tbd>
ns
th(Q)
data output hold time
in SPI mode
[2]
-
<tbd>
ns
SSP slave
tDS
data set-up time
in SPI mode
[3][4]
<tbd>
-
ns
tDH
data hold time
in SPI mode
[3][4]
<tbd>
 T
cy(PCLK) +
<tbd>
-ns
tv(Q)
data output valid time
in SPI mode
[3][4]
-<tbd>
 T
cy(PCLK) +
<tbd>
ns
th(Q)
data output hold time
in SPI mode
[3][4]
-<tbd>
 T
cy(PCLK) +
<tbd>
ns



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