 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
OMAP3530ECBBA データシート(PDF) 155 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
OMAP3530ECBBA データシート(HTML) 155 Page - Texas Instruments |
|
|
155 / 264 page  6.4 External Memory Interfaces 6.4.1 General-Purpose Memory Controller (GPMC) 6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 The OMAP3530/25 processor includes the following external memory interfaces: • General-purpose memory controller (GPMC) • SDRAM controller (SDRC) The GPMC is the OMAP3530/25 unified memory controller used to interface external memory devices such as: • Asynchronous SRAM-like memories and ASIC devices • Asynchronous page mode and synchronous burst NOR flash • NAND flash Table 6-3 and Table 6-4 assume testing over the recommended operating conditions (see Figure 6-2 through Figure 6-5) and electrical characteristic conditions. Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 1.8 ns tF Input signal fall time 1.8 ns Output Conditions CLOAD Output load capacitance 15.94 pF Table 6-3. GPMC/NOR Flash Interface Timing Requirements – Synchronous Mode(1) NO. PARAMETER OPP3 OPP2 OPP1(2) UNIT MIN MAX MIN MAX MIN MAX F12 tsu(DV-CLKH) Setup time, read gpmc_d[15:0] 1.9 1.9 3.2 ns valid before gpmc_clk high F13 th(CLKH-DV) Hold time, read gpmc_d[15:0] 1.9 1.9 1.9 ns valid after gpmc_clk high F21 tsu(WAITV-CLKH) Setup time, gpmc_waitx(3) valid 1.9 1.9 3.2 ns before gpmc_clk high F22 th(CLKH-WAITV) Hold Time, gpmc_waitx(3) valid 2.5 2.5 2.5 ns after gpmc_clk high (1) For VDD2 (vdd_core) OPP voltages, see Table 3-3, Recommended Operating Conditions. (2) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1. (3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see the OMAP35x Technical Reference Manual (literature number SPRUF988). Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode NO. PARAMETER 1.15 V 1.0 V 0.9 V UNIT MIN MAX MIN MAX MIN MAX F0 tc(CLK) Cycle time(15), output 10 12.05 25 ns clock gpmc_clk period F1 tw(CLKH) Typical pulse duration, 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) ns output clock gpmc_clk high F1 tw(CLKL) Typical pulse duration, 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) ns output clock gpmc_clk low tdc(CLK) Duty cycle error, output –500 500 –602 602 –1250 1250 ps clk gpmc_clk Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 155 |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
