OMAP3530ECBBA datasheet(142/264 Pages) TI1

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4.3.1.1 DPLL1 (MPU)

4.3.1.2 DPLL2 (IVA2)

4.3.1.3 DPLL3 (CORE)

4.3.1.4 DPLL4 (Peripherals)

4.3.1.5 DPLL5 (Second peripherals DPLL)

4.3.2

Delay-Locked Loops (DLL)

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

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• Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of

1-MHz noise

• Up to five independent output dividers for simultaneous generation of multiple clock frequencies

DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem

clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3

(CORE DPLL) output as a high-frequency bypass input clock.

DPLL2 is located in the IVA subsystem and supplies all clocks of the subsystem. All IVA subsystem clocks

are internally generated in the subsystem. When the core domain is on, it can use the DPLL3 (CORE

DPLL) output as a high-frequency bypass input clock.

DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the

emulation trace clock. It is located in the core domain area. All interface clocks and a few module

functional clocks are generated in the CM. When the core domain is on, it can be used as a bypass input

to DPLL1 and DPLL2.

DPLL4 generates clocks for the peripherals. It supplies five clock sources: 96-MHz functional clocks to

subsystems and peripherals, 54 MHz to TV DAC, display functional clock, camera sensor clock, and

emulation trace clock. It is located in the core domain area. All interface clocks and few module functional

clocks are generated in the CM. Its outputs to the DSS, PER, and EMU domains are propagated with

always-on clock trees.

DPLL5 supplies the 120-MHz functional clock to the CM.

The SDRC includes analog-controlled delay technology for interfacing high-speed mobile DDR memory

components. For more information, see the SDRC-GPMC chapter of the OMAP35x Technical Reference

Manual (TRM) [literature number SPRUF98]. A DLL is a calibration module used on dynamic track of

voltage and temperature variations, as well as to compensate the silicon process dispersion.

The SDRC DLL has four modes of operation:

1. APPLICATION MODE 0: used to generate 72

° delay

2. APPLICATION MODE 1: used to generate 90

° delay

3. MODEMAXDELAY: used for low frequency operation where we do not have the requirement of

accurate 72

° or 90° phase shift

4. IDLE MODE: a low-power state that allows the DLL to gain lock quickly on exit from this mode

142

CLOCK SPECIFICATIONS

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