© 2005 Fairchild Semiconductor Corporation

DS005069

www.fairchildsemi.com

September 1983

Revised January 2005

MM74HC04

Hex Inverter

General Description

The MM74HC04 inverters utilize advanced silicon-gate

CMOS technology to achieve operating speeds similar to

LS-TTL gates with the low power consumption of standard

CMOS integrated circuits.

The MM74HC04 is a triple buffered inverter. It has high

noise immunity and the ability to drive 10 LS-TTL loads.

The 74HC logic family is functionally as well as pin-out

compatible with the standard 74LS logic family. All inputs

are protected from damage due to static discharge by inter-

Features

s Typical propagation delay: 8 ns

s Fan out of 10 LS-TTL loads

s Quiescent power consumption: 10

µW maximum at

room temperature

s Low input current: 1

µA maximum

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Logic Diagram

1 of 6 Inverters

Order Number

Package

Package Description

Number

MM74HC04M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MM74HC04M_NL

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MM74HC04SJ

M14D

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC04MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC04MTC_NL

MTC14

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

MM74HC04N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

MM74HC04N_NL

N14A

Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide