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A3P030 データシート(PDF) 101 Page - Microsemi Corporation |
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A3P030 データシート(HTML) 101 Page - Microsemi Corporation |
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101 / 220 page  ProASIC3 Flash Family FPGAs Revision 13 2-87 Table 2-111 • A3P250 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 0.80 1.01 0.91 1.15 1.07 1.36 ns tRCKH Input High Delay for Global Clock 0.78 1.04 0.89 1.18 1.04 1.39 ns tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-112 • A3P400 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 0.871.090.991.241.171.46 ns tRCKH Input High Delay for Global Clock 0.86 1.11 0.98 1.27 1.15 1.49 ns tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. |
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