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AM79C978VC/W データシート(PDF) 225 Page - Advanced Micro Devices |
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AM79C978VC/W データシート(HTML) 225 Page - Advanced Micro Devices |
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225 / 261 page  Am79C978 225 SWITCHING CHARACTERISTICS: BUS INTERFACE (CONTINUED) External Clock (XTAL) Timing Specifications External Clock (Oscillator) Timing Specification Figure 52. Clock Timing PMD Interface PECL Note: 1. Not included in the production test. Figure 53. PMD Interface Timing (PECL) Clock Timing No. Symbol Parameter Description Min Max Unit 1tPER Cycle time 49.995 50.005 ns 2tPWH Cycle high time 0.4* Tcycle 0.6*Tcycle ns 3tPWL Clock low time 0.4*Tcycle 0.6*Tcycle ns Clock Timing No. Symbol Parameter Description Min Max Unit 1tPER Cycle time 16.665 16.669 ns 2tPWH Cycle high time 0.4* Tcycle 0.6*Tcycle ns 3tPWL Clock low time 0.4*Tcycle 0.6*Tcycle ns XCLK 1 3 2 22206B-55 No. Symbol Parameter Description Test Conditions Min Max Unit 160 tR (Note 1) TX+, TX- Rise Time PECL Load 0.5 3 ns 161 tF (Note 1) TX+, TX- Fall Time PECL Load 0.5 3 ns 162 tSK (Note 1) TX+ to TX- skew PECL Load -- +200 ps 163 tS SDI setup time to XCLK high -- 7 -- ns 164 tH SDI hold time to XCLK high -- 5 -- ns TX+,TX– TX+ TX– 162 161 80% 20% 160 22206B-56 |
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