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AM8530 データシート(PDF) 115 Page - Advanced Micro Devices

部品番号 AM8530
部品情報  Serial Communications Controller
PDF  194 Pages
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メーカー  AMD [Advanced Micro Devices]
ホームページ  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM8530 データシート(HTML) 115 Page - Advanced Micro Devices

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Register Description
AMD
6–5
6.2
WRITE REGISTERS
The SCC write register set for each channel includes ten control registers, two sync char-
acter registers, two baud rate time constant registers, a transmit buffer, and a master in-
terrupt register. The following sections describe in detail each write register and the
associated bit configuration for each.
6.2.1
Write Register 0 (Command Register)
WR0 is the command register and the CRC reset code register. Figure 6–1 shows the bit
configuration for WR0.
D7 D6 D5 D4 D3 D2 D1 D0
00
00
01
01
00
01
10
11
Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
0
1
0
1
Register 0
Register 1
Register 2
Register 3
10
10
11
11
0
1
0
1
Register 4
Register 5
Register 6
Register 7
00
00
01
01
0
1
0
1
Register 8
Register 9
Register 10
Register 11
10
10
11
11
0
1
0
1
Register 12
Register 13
Register 14
Register 15
00
00
01
0
1
0
01
10
10
11
1
0
1
0
11
1
Null Code
Point High
Reset EXT/Status Interrupts
Send Abort (SDLC)
Enable INT On Next Rx Character
Reset TxINT Pending
Error Reset
Reset Highest IUS
With Point High Command
Figure 6–1. Write Register 0



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