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STM32F215RG データシート(PDF) 111 Page - STMicroelectronics

部品番号 STM32F215RG
部品情報  ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/1284KB RAM
PDF  175 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
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STM32F215RG データシート(HTML) 111 Page - STMicroelectronics

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STM32F21xxx
Electrical characteristics
174
I2S - SPI interface characteristics
Unless otherwise specified, the parameters given in Table 53 for SPI or in Table 54 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 13.
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 53. SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
SPI1 master/slave mode
-
30
MHz
SPI2/SPI3 master/slave mode
-
15
tr(SCL)
tf(SCL)
SPI clock rise and fall
time
Capacitive load: C = 30 pF,
fPCLK = 30 MHz
-
8
ns
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
30
70
%
tsu(NSS)(1)
1. Based on characterization, not tested in production.
NSS setup time
Slave mode
4tPCLK
-
ns
th(NSS)(1)
NSS hold time
Slave mode
2tPCLK
-
tw(SCLH)(1)
tw(SCLL)(1)
SCK high and low time
Master mode, fPCLK = 30 MHz,
presc = 2
tPCLK-3tPCLK+3
tsu(MI) (1)
tsu(SI)(1)
Data input setup time
Master mode
5
-
Slave mode
5
-
th(MI) (1)
th(SI)(1)
Data input hold time
Master mode
5
-
Slave mode
4
-
ta(SO)(1)(2)
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access
time
Slave mode, fPCLK = 30 MHz
0
3tPCLK
tdis(SO)(1)(3)
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable
time
Slave mode
2
10
tv(SO) (1)
Data output valid time Slave mode (after enable edge)
-
25
tv(MO)(1)
Data output valid time Master mode (after enable edge)
-
5
th(SO)(1)
Data output hold time
Slave mode (after enable edge)
15
-
th(MO)(1)
Master mode (after enable edge)
2
-



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