AT24C32/64

7

Device Addressing

The 32K/64K EEPROM requires an 8-bit device address

word following a start condition to enable the chip for a read

or write operation (refer to Figure 1). The device address

word consists of a mandatory one, zero sequence for the

first four most significant bits as shown. This is common to

all 2-wire EEPROM devices.

The 32K/64K uses the three device address bits A2, A1, A0

to allow as many as eight devices on the same bus. These

bits must compare to their corresponding hardwired input

pins. The A2, A1, and A0 pins use an internal proprietary

circuit that biases them to a logic low condition if the pins

are allowed to float.

The eighth bit of the device address is the read/write opera-

tion select bit. A read operation is initiated if this bit is high

and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will

output a zero. If a compare is not made, the device will

return to standby state.

NOISE PROTECTION: Special internal circuitry placed on

the SDA and SCL pins prevent small noise spikes from

resets the device to prevent data corruption in a noisy envi-

ronment.

DATA SECURITY: The AT24C32/64 has a hardware data

protection scheme that allows the user to write protect the

upper quadrant (8/16K bits) of memory when the WP pin is

at V

Write Operations

BYTE WRITE: A write operation requires two 8-bit data

word addresses following the device address word and

acknowledgment. Upon receipt of this address, the

EEPROM will again respond with a zero and then clock in

the first 8-bit data word. Following receipt of the 8-bit data

word, the EEPROM will output a zero and the addressing

device, such as a microcontroller, must terminate the write

sequence with a stop condition. At this time the EEPROM

enters an internally-timed write cycle, t

memory. All inputs are disabled during this write cycle and

the EEPROM will not respond until the write is complete

(refer to Figure 2).

PAGE WRITE: The 32K/64K EEPROM is capable of 32-

byte page writes.

A page write is initiated the same way as a byte write, but

the microcontroller does not send a stop condition after the

first data word is clocked in. Instead, after the EEPROM

acknowledges receipt of the first data word, the microcon-

troller can transmit up to 31 more data words. The

EEPROM will respond with a zero after each data word

received. The microcontroller must terminate the page

write sequence with a stop condition (refer to Figure 3).

The data word address lower 5 bits are internally incre-

mented following the receipt of each data word. The higher

data word address bits are not incremented, retaining the

memory page row location. When the word address, inter-

nally generated, reaches the page boundary, the following

byte is placed at the beginning of the same page. If more

than 32 data words are transmitted to the EEPROM, the

data word address will “roll over” and previous data will be

overwritten.

ACKNOWLEDGE POLLING: Once the internally-timed

write cycle has started and the EEPROM inputs are dis-

abled, acknowledge polling can be initiated. This involves

sending a start condition followed by the device address

word. The read/write bit is representative of the operation

desired. Only if the internal write cycle has completed will

the EEPROM respond with a zero, allowing the read or

write sequence to continue.

Read Operations

Read operations are initiated the same way as write opera-

tions with the exception that the read/write select bit in the

device address word is set to one. There are three read

operations: current address read, random address read

and sequential read.

CURRENT ADDRESS READ: The internal data word

address counter maintains the last address accessed dur-

ing the last read or write operation, incremented by one.

This address stays valid between operations as long as the

chip power is maintained. The address “roll over” during

read is from the last byte of the last memory page, to the

first byte of the first page. The address “roll over” during

write is from the last byte of the current page to the first

byte of the same page.

Once the device address with the read/write select bit set

to one is clocked in and acknowledged by the EEPROM,

the current address data word is serially clocked out. The

microcontroller does not respond with an input zero but

does generate a following stop condition (refer to Figure 4).

RANDOM READ: A random read requires a “dummy” byte

write sequence to load in the data word address. Once the

device address word and data word address are clocked in

and acknowledged by the EEPROM, the microcontroller

must generate another start condition. The microcontroller

now initiates a current address read by sending a device

address with the read/write select bit high. The EEPROM

acknowledges the device address and serially clocks out

the data word. The microcontroller does not respond with a

zero but does generate a following stop condition (refer to

Figure 5).

SEQUENTIAL READ: Sequential reads are initiated by

either a current address read or a random address read.

After the microcontroller receives a data word, it responds

with an acknowledge. As long as the EEPROM receives an