PIC16F72SLASHSS datasheet(130/136 Pages) MICROCHIP

130 / 136 page

PIC16F72

DS39597B-page 128

 2002 Microchip Technology Inc.

Registers ............................................................................. 36

ADCON0 (A/D Control 0) ............................................ 53

ADCON1 (A/D Control 1) ............................................ 54

CCPCON1 (Capture/Compare/PWM Control 1) ......... 37

Initialization Conditions (table) .................................... 66

INTCON (Interrupt Control) ......................................... 14

OPTION ...................................................................... 13

PCON (Power Control) ............................................... 17

PIE1 (Peripheral Interrupt Enable 1) ........................... 15

PIR1 (Peripheral Interrupt Flag 1) ............................... 16

PMCON1 (Program Memory Control 1) ...................... 27

SSPCON (Sync Serial Port Control) ........................... 45

SSPSTAT (Synchronous Serial Port Status) ............... 44

STATUS ...................................................................... 12

Summary....................................................................... 9

T1CON (Timer1 Control) ............................................. 31

RESET .......................................................................... 59, 62

Brown-out Reset (BOR). See Brown-out Reset (BOR)

MCLR RESET. See MCLR

Power-on Reset (POR). See Power-on Reset (POR)

RESET Conditions for All Registers............................ 66

RESET Conditions for PCON Register ....................... 65

RESET Conditions for Program Counter .................... 65

RESET Conditions for STATUS Register .................... 65

WDT Reset. See Watchdog Timer (WDT)

Revision History ................................................................ 123

RP0, RP1 bit ......................................................................... 7

S.......................................................................................... 44

Sales and Support............................................................. 133

Slave Mode

SCL ............................................................................. 48

SDA............................................................................. 48

SLEEP..................................................................... 59, 62, 71

SMP .................................................................................... 44

Software Simulator (MPLAB SIM)....................................... 82

Special Event Trigger.......................................................... 57

Special Features of the CPU............................................... 59

Special Function Registers

PMADRH .................................................................... 27

PMADRL ..................................................................... 27

PMCON1..................................................................... 27

PMDATH ..................................................................... 27

PMDATL...................................................................... 27

SPI

Associated Registers .................................................. 46

SPI Clock Edge Select bit, CKE.......................................... 44

SPI Data Input Sample Phase Select bit, SMP................... 44

SPI Mode

Serial Clock ................................................................. 43

Serial Data In .............................................................. 43

Serial Data Out............................................................ 43

Slave Select ................................................................ 43

SSP

ACK............................................................................. 48

Addressing .................................................................. 48

BF bit........................................................................... 48

I2C Mode Operation .................................................... 48

R/W bit ........................................................................ 49

Reception .................................................................... 49

SCL Clock Input .......................................................... 48

SSPOV bit ................................................................... 48

Transmission ............................................................... 49

SSPADD Register............................................................... 10

SSPEN................................................................................ 45

SSPIF ................................................................................. 16

SSPM3:SSPM0 .................................................................. 45

SSPOV ............................................................................... 45

SSPSTAT Register ............................................................. 10

Stack................................................................................... 19

Overflows.................................................................... 19

Underflow ................................................................... 19

START bit, S....................................................................... 44

STATUS Register

DC bit.......................................................................... 12

IRP bit ......................................................................... 12

PD bit .......................................................................... 62

TO bit .................................................................... 12, 62

STOP bit, P......................................................................... 44

Synchronous Serial Port (SSP) .......................................... 43

Overview..................................................................... 43

SPI Mode .................................................................... 43

Synchronous Serial Port Enable bit, SSPEN ...................... 45

Synchronous Serial Port Interrupt....................................... 16

Synchronous Serial Port Mode Select bits,

SSPM3:SSPM0 ............................................................ 45

T2CKPS0 bit ....................................................................... 36

T2CKPS1 bit ....................................................................... 36

T2CON (Timer2 Control) .................................................... 36

TAD...................................................................................... 56

Timer0................................................................................. 29

Clock Source Edge Select (T0SE bit)......................... 13

Clock Source Select (T0CS bit) .................................. 13

External Clock............................................................. 30

Interrupt ...................................................................... 29

Operation .................................................................... 29

Overflow Enable (TMR0IE bit) .................................... 14

Overflow Flag (TMR0IF bit) ........................................ 69

Overflow Interrupt ....................................................... 69

Prescaler .................................................................... 30

T0CKI ......................................................................... 30

Timer1

Associated Registers .................................................. 34

Asynchronous Counter Mode ..................................... 33

Capacitor Selection..................................................... 33

Counter Operation ...................................................... 32

Interrupt ...................................................................... 33

Operation in Timer Mode ............................................ 32

Oscillator..................................................................... 33

Prescaler .................................................................... 34

Resetting TMR1H, TMR1L Register Pair.................... 34

Resetting Using a CCP Trigger Output....................... 33

Synchronized Counter Mode ...................................... 32

Timer2................................................................................. 35

Interrupt ...................................................................... 35

Operation .................................................................... 35

Output ......................................................................... 35

Prescaler, Postscaler .................................................. 35

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