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Table 4-35. IRQ Wakeup Status Mapping

(0x30-0x3F)

SETUP_

DATA

Function

Do not wakeup on IRQ activity.

0x0a

Assign IRQ Wake to bit 10 in PM1A_STS register

0x10

Assign IRQ Wake to bit 0 in GPE0_STS register

0x11

Assign IRQ Wake to bit 1 in GPE0_STS register

0x12

Assign IRQ Wake to bit 2 in GPE0_STS register

0x13

Assign IRQ Wake to bit 3 in GPE0_STS register

0x14

Assign IRQ Wake to bit 4 in GPE0_STS register

0x15

Assign IRQ Wake to bit 5 in GPE0_STS register

0x16

Assign IRQ Wake to bit 6 in GPE0_STS register

0x17

Assign IRQ Wake to bit 7 in GPE0_STS register

0x18

Assign IRQ Wake to bit 8 in GPE0_STS register

0x19

Assign IRQ Wake to bit 9 in GPE0_STS register

0x1A

Assign IRQ Wake to bit 10 in GPE0_STS register

0x1B

Assign IRQ Wake to bit 11 in GPE0_STS register

0x1C

Assign IRQ Wake to bit 12 in GPE0_STS register

0x1D

Assign IRQ Wake to bit 13 in GPE0_STS register

0x1E

Assign IRQ Wake to bit 14 in GPE0_STS register

0x1F

Assign IRQ Wake to bit 15 in GPE0_STS register

Note: When the ability to wakeup on an IRQ is desired use

indexes 0x31 through 0x3F. This will allow sensing of

interrupts while sleeping and waking of the system

when activity occurs. The desired GPE0 Status bit will

only be set if the system is sleeping and a wake event

occurs. The system will only wake if the status bit is

enabled in the corresponding enable register.

IRQ8 (RTC) is assigned to the RTC_STS bit in the

PM1A_STS register by default and should NOT be

changed.

For enabling and selection of the GPE0 Status bit to be

set when Wake on IRQ Activity is desired, use the

SETUP_DATA values listed above.

Table 4-36. Commands

(0x41-0x43, and 0x50)

Index

Function

0x41

Configure IRQ to be used for SCI: When map-

ping the SCI interrupt SETUP_IDX contains the

number of the IRQ to be used for the SCI. Valid

values are 3-7, 9-12, and 14-15. Invalid values will

not change the assignment of the SCI IRQ. The

default value for the SCI IRQ is 9.

0x42

Enable Reads of ACPI Registers: Prior to the

issuance of this command only WRITES can be

performed to the V-ACPI Fixed feature registers.

This command MUST be issued to enable reading

of the registers. This is to prevent the User Def 1

hook on NON-ACPI systems from interfering with

system functions.

0x43

Do Atomic I/O Sequence: This command allows

a sequence of I/O operations to be done with no

interruption. Certain SuperI/O chips must receive

unlock codes with NO intervening I/O. In addition

other SuperI/O chips do not allow I/O to devices

while in configuration mode. This command will

insure that I/O operations are completed without

interruption. The address of a sequence of I/O

commands is placed in the SETUP_DATA regis-

ter. The command sequence will then be pro-

cessed immediately.

The I/O command sequence consists of two parts:

the signature/length block and the I/O block.

There is only one signature/length block. There

may be one or more I/O blocks.

The signature block consists of four DWORDs

(see Table 4-37).

The I/O block consists of four bytes followed by

three DWORDs (see Table 4-38).

0x50

Video Power: This command will control the

power to the SOFTVGA. If SETUP_DATA is writ-

ten with a 0, power will be turned off. If a 1 is writ-

ten, power will be turned on.

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