TNETX3150A datasheet(110/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

110

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels

are compatible with TTL devices.

Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,

the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low

is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level

at which the signal is said to be high is 2 V, as shown in the following.

The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically

1.5 ns.

0.8 V (low)

2 V (high)

test measurement

The test-load circuit shown in Figure 52 represents the programmable load of the tester pin electronics that is

used to verify timing parameters of the TNETX3150/TNETX3150A output signals.

TTL OUTPUT TEST LOAD

IOH

VLOAD

IOL

Point

Test

Under

Output

TTL

Where: IOH

Refer to IOH in recommended operating conditions.

IOL

Refer to IOL in recommended operating conditions.

VLOAD =

1.5 V, typical dc-level verification or

0.7 V, typical timing verification

18 pF, typical load-circuit capacitance

Figure 52. Test and Load Circuit

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