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ST92196A データシート(PDF) 191 Page - STMicroelectronics |
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ST92196A データシート(HTML) 191 Page - STMicroelectronics |
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191 / 268 page  191/268 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) Bit 2 = CPHA: Transmission Clock Phase. CPHA controls the relationship between the data on the SDI and SDO pins, and the clock signal on the SCK pin. The CPHA bit selects the clock edge used to capture data. It has its greatest impact on the first bit transmitted (MSB), because it does (or does not) allow a clock transition before the first data capture edge. Figure 81 shows the relation- ship between CPHA, CPOL and SCK, and indi- cates active clock edges and strobe times. Bit 1:0 = SPR[1:0]: SPI Rate. These two bits select one (of four) baud rates, to be used as SCK. Figure 81. SPI Data and Clock Timing CPOL CPHA SCK (in Figure 81) 0 0 1 1 0 1 0 1 (a) (b) (c) (d) SPR1 SPR0 Clock Divider SCK Frequency (@ INTCLK = 24MHz) 0 0 1 1 0 1 0 1 8 16 128 256 3000kHz 1500kHz 187.5kHz 93.75kHz (T = 0.33 µs) (T = 0.67 µs) (T = 5.33 µs) (T = 10.66 µs) |
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