ST72774 datasheet(110/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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DDC INTERFACE (Cont’d)

4.8.6 Register Description

DDC CONTROL REGISTER (CR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE

Peripheral enable.

This bit is set and cleared by software.

0: Peripheral disabled

1: Slave capability

Notes:

– When PE=0, all the bits of the CR register and

the SR register are reset. All outputs are re-

leased while PE=0

– When PE=1, the corresponding I/O pins are se-

lected by hardware as alternate functions.

– To enable the I2C interface, write the CR register

TWICE with PE=1 as the first write only activates

the interface (only PE is set).

Bit 4 = EDDCEN

Enhanced DDC address

detection enabled.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disabled

(PE=0). The 60h/61h Enhanced DDC address is

acknowledged.

0: Enhanced DDC address detection disabled

1: Enhanced DDC address detection enabled

Bit 3 = Reserved. Forced to 0 by hardware.

Bit 2 = ACK

Acknowledge enable.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disabled

(PE=0).

0: No acknowledge returned

1: Acknowledge returned after an address byte or

a data byte is received

Bit 1 = STOP

Release I2C bus.

This bit is set and cleared by software or when the

interface is disabled (PE=0).

– Slave Mode:

0: Nothing

1: Release the SCL and SDA lines after the cur-

rent byte transfer (BTF=1). The STOP bit has to

be cleared by software.

Bit 0 = ITE

Interrupt enable.

This bit is set and cleared by software and cleared

by hardware when the interface is disabled

(PE=0).

0: Interrupts disabled

1: Interrupts enabled

Refer to Figure 68 for the relationship between the

events and the interrupt.

SCL is held low when the BTF or ADSL is detect-

ed.

EDDC

0ACK

STOP

ITE

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