STM32F413CG datasheet(114/207 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F413xG/H

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DocID029162 Rev 2

6.3.10

PLL characteristics

The parameters given in Table 46 and Table 47 are derived from tests performed under

temperature and VDD supply voltage conditions summarized in Table 16.

Table 46. Main PLL characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLL_IN

PLL input clock(1)

-0.95(2)

12.10

MHz

fPLLP_OUT

PLLP multiplier output clock

100

fPLLQ_OUT

48 MHz PLLQ multiplier

output clock

fPLLR_OUT

PLLR multiplier output clock

for I2S and SAI

216

fVCO_OUT

PLL VCO output

100

432

tLOCK

PLL lock time

VCO freq = 100 MHz

200

µs

VCO freq = 432 MHz

100

300

Jitter(3)

Cycle-to-cycle jitter

System clock

100 MHz

RMS

peak

±150

Period Jitter

RMS

peak

±200

Bit Time CAN jitter

Cycle to cycle at 1 MHz

on 1000 samples.

330

IDD(PLL)(4)

PLL power consumption on VDD

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLL)(4)

PLL power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared

between PLL and PLLI2S.

2. Guaranteed by design.

3. The use of two PLLs in parallel could degraded the Jitter up to +30%.

4. Guaranteed by characterization.

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