AT89C51CC03U-RDTIM datasheet(116/195 Pages) ATMEL

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116

AT89C51CC03

4182I–CAN–06/05

Table 61. CANBT2 Register

CANBT2 (S:B5h)

CAN Bit Timing Registers 2

Note:

The CAN controller bit timing registers must be accessed only if the CAN controller is dis-

abled with the ENA bit of the CANGCON register set to 0.

See Figure 52.

No default value after reset.

543

210

SJW 1

SJW 0

PRS 2

PRS 1

PRS 0

Bit

Number

Bit Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6-5

SJW1:0

Re-synchronization Jump Width

To compensate for phase shifts between clock oscillators of different bus

controllers, the controller must re-synchronize on any relevant signal edge of

the current transmission.

The synchronization jump width defines the maximum number of clock cycles.

A bit period may be shortened or lengthened by a re-synchronization.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3-1

PRS2:0

Programming Time Segment

This part of the bit time is used to compensate for the physical delay times

within the network. It is twice the sum of the signal propagation time on the

bus line, the input comparator delay and the output driver delay.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Tsjw = Tscl x (SJW [1..0] +1)

Tprs = Tscl x (PRS[2..0] + 1)

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