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STM32F411RET6 データシート(PDF) 118 Page - STMicroelectronics |
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STM32F411RET6 データシート(HTML) 118 Page - STMicroelectronics |
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118 / 149 page ![]() Electrical characteristics STM32F411xC STM32F411xE 118/149 DocID026289 Rev 6 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 42 or Figure 43, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. |
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