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TNETV6446AINZWT データシート(PDF) 175 Page - Texas Instruments

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部品番号 TNETV6446AINZWT
部品情報  Digital Media System-on-Chip
PDF  227 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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TNETV6446AINZWT データシート(HTML) 175 Page - Texas Instruments

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PCLK
(Positive Edge Clocking)
9
PCLK
(Negative Edge Clocking)
10
VCTL(A)
A. VCTL = HSYNC and VSYNC
VPBECLK
27
28
33
34
35
36
LCD_FIELD
TMS320DM6446
www.ti.com
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
Table 6-61. Timing Requirements for VPBE Control Input With Respect to PCLK and VPBECLK(1) (see
Figure 6-51)
A-513,
-594,
NO.
UNIT
-810
MIN
MAX
9
tsu(VCTLV-PCLK)
Setup time, VCTL valid before PCLK edge
2
ns
10
th(PCLK-VCTLV)
Hold time, VCTL valid after PCLK edge
0.5
ns
27
tsu(VCTLV-VPBECLK)
Setup time, VCTL valid before VPBECLK rising edge
2
ns
28
th(VPBECLK-VCTLV)
Hold time, VCTL valid after VPBECLK rising edge
0.5
ns
33
tsu(FIELD-PCLK)
Setup time, LCD_FIELD valid before PCLK edge
5P(2)
ns
34
th(PCLK-FIELD)
Hold time, LCD_FIELD valid after PCLK edge
5P(2)
ns
35
tsu(FIELD-VPBECLK)
Setup time, LCD_FIELD valid before VPBECLK edge
5P(2)
ns
36
th(VPBECLK-FIELD)
Hold time, LCD_FIELD valid after VPBECLK edge
5P(2)
ns
(1)
PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising
edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.
(2)
P = 1/(VCLKIN clock frequency) in ns. VCLKIN is either PCLK or VPBECLK, whichever is used.
Figure 6-51. VPBE Input Timing With Respect to PCLK and VPBECLK
Copyright © 2005–2010, Texas Instruments Incorporated
Peripheral and Electrical Specifications
175
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6446



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