DESCRIPTION
The ST2305 is the P-Channel logic enhancement mode power field effect transistor are produced using high cell density, DMOS trench technology.
This high density process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other batter powered circuits, and low in-line power loss are needed in a very small outine surface mount package.

FEATURE
● -10V/-3.5A, RDS(ON) = 50m-ohm @VGS = -4.5V
● -10V/-3.0A, RDS(ON) = 70m-ohm @VGS = -2.5V
● -10V/-2.0A, RDS(ON)= 105m-ohm @VGS=-1.8V
● Super high density cell design for extremely low RDS(ON)
● Exceptional on-resistance and maximum DC current capability
● SOT-23-3L package design