Description
The TC51832AP is a 256K bit high speed CMOS pseudo static RAM organized as 32,768 words by 8 bits. The TC51832AP utilizes
a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power storage. The
TC51832AP operates from a single 5V power supply. Refreshing is supported by a refresh (RFSH) input which enables two types of
refreshing - auto refresh and self refresh. The TC51832AP features a static RAM-like interface with a write cycle in which the input
data is written into the memory cell at the rising edge of RW thus simplifying the microprocessor interface.
The TC51832AP is pin-compatible with the 256K bit CMOS static RAM JEDEC standard and is available in a 28-pin, 0.6 inch
and 0.3 inch width plastic DIP, and a small outline plastic flat package.

Features
• Organization: 32,768 words x 8 bits
• Single 5V power supply
• Fast access time
tCEA CE Access Time
TOEA OE Access Time
tac Cycle Time
Power Dissipation
Self Refresh Current
-70
70ns
30ns
115ns
385mW
TC51832A Family
- TC51832AP/APL
TC51832ASP/ASPL
TC51832AF/AFL
-85
85ns
35ns
135ns
303mW
1mA/100μA
Self refresh is supported by an internal timer
• Inputs and outputs TTL compatible
• Auto refresh is supported by an internal refresh address
counter
• Refresh: 256 refresh cycles/4ms
• Pin compatible: 256K SRAM (JEDEC)
• Package
-10
100ns
40ns
: DIP28-P-600
: DIP28-P-300B
: SOP28-P-450
160ns
248mW