Functional Description
• 3-to-8 Line Decoder/Latch
General
The 74HC237D is a high speed CMOS 3-to-8 DECODER ADDRESS LATCH fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power
dissipation.
It is composed of a 3-bit input latches with a common GL enable input and 3-to-8 line decoder with enable inputs
G1 and G2. The 3-bit binary data is stored into the input latch on the high level of GL. The value of this data
determines which one of the outputs will go low.
When the enable input G1 is held low or G2 is held high, decoding function is inhibited and all the 8 outputs go
high. The two enable inputs are provided to ease cascade connection and permits the application address decoder
for memory system.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features
(1) High speed: tpd = 12 ns (typ.) at VCC = 5 V
(2) Low power dissipation: ICC = 4.0 μA (max) at Ta = 25 
(3) Balanced propagation delays: tPLH ≈ tPHL
(4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V