HARDWARE MANUAL
The XRT79L74 is a four channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controllers and Line Interface Units with Jitter Attenuators that are designed to support ATM direct mapping and cell delineation as well as PPP mapping and Frame processing.

GENERAL FEATURES:
• Integrated T3/E3 Line Interface Unit
• Integrated Jitter Attenuator that can be selected either in Receive or Transmit path
• Flexible integrated Clock Multiplier that takes single frequency clock and generates either DS3 or E3 frequency.
• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY Interface operating at 25, 33 or 50 MHz.
• HDLC Controller that provides the mapping/extraction of either bit or byte mapped encapsulated packet from DS3/E3 Frame.
• Contains on-chip 16 cell FIFO (configurable in depths of 4, 8, 12 or 16 cells), in both the Transmit (TxFIFO) and Receive Directions (RxFIFO)
• Contains on-chip 54 byte Transmit and Receive OAM Cell Buffer for transmission, reception and processing of OAM Cells
• Supports ATM cell or PPP Packet Mapping
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3/E3 Clear-Channel Framing.
• Includes PRBS Generator and Receiver
• Supports Line, Cell, and PLCP Loop-backs
• Interfaces to 8 Bit wide Intel, Motorola or PowerPC
• Low power 3.3V, 5V Input Tolerant, CMOS
• Available in 456 Lead PBGA Package
• JTAG Interface

APPLICATIONS
• Digital Access and Cross Connect Systems
• 3G Base Stations
• DSLAMs
• Digital, ATM, WAN and LAN Switches