• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA
bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa
• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport
front end (MPFE) of the HPS SDRAM controller
• Arm CoreSight™ JTAG debug access port, trace port, and on-chip trace storage