Features
• Modular Architecture
• Low-Power Central Processing Unit (CPU32L)
— Virtual memory implementation
— Loop mode of instruction execution
— Improved exception handling for controller applications
— Table lookup and interpolate instruction
— CPU-only LPSTOP operation/normal MCU LPSTOP operation
• Low-Power System Integration Module (SIML)
— External bus support
— Twelve programmable chip-select outputs
— System protection logic
— On-chip PLL for system clock
— Watchdog timer, clock monitor, and bus monitor
— Expanded LPSTOP operation
• Queued Serial Module (QSM)
— Enhanced serial communication interface (SCI)
— Queued serial peripheral interface (QSPI)
— Dual function I/O ports
• Configurable Timer Module 6 (CTM6)
— One bus interface unit submodule (BIUSM)
— One counter prescaler submodule (CPSM)
— Three modulus counter submodules (MCSM)
— One free-running counter submodule (FCSM)
— Eleven double action submodules (DASM)
— Four (eight channels) single action submodules (SASM)
— One real time clock submodule (RTCSM)
— One port I/O submodule (PIOSM)
— Two 32-byte RAM submodules (RAMSM)