PowerPC 601 Microprocessor Features
This section describes details of the 601’s implementation of the PowerPC architecture. Major features of
the 601 are as follows:
• High-performance, superscalar microprocessor
— As many as three instructions in execution per clock (one to each of the three execution units)
— Single clock cycle execution for most instructions
— Pipelined FPU for all single-precision and most double-precision operations
• Three independent execution units and two register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for single- or double-precision operands
• High instruction and data throughput
— Zero-cycle branch capability
— Programmable static branch prediction on unresolved conditional branches
— Instruction unit capable of fetching eight instructions per clock from the cache
— An eight-entry instruction queue that provides look-ahead capability
— Interlocked pipelines with feed-forwarding that control data dependencies in hardware
— Unified 32-Kbyte cache—eight-way set-associative, physically addressed; LRU replacement
algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— Memory unit with a two-element read queue and a three-element write queue
— Run-time reordering of loads and stores
— BPU that performs condition register (CR) look-ahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 256-entry, two-way set-associative UTLB
— Four-entry BAT array providing 128-Kbyte to 8-Mbyte blocks
— Four-entry, first-level ITLB
— Hardware table search (caused by UTLB misses) through hashed page tables
— 52-bit virtual address; 32-bit physical address
• Facilities for enhanced system performance
— Bus speed defined as selectable division of operating frequency
— A 64-bit split-transaction external data bus with burst transfers
— Support for address pipelining and limited out-of-order bus transactions
— Snooped copyback queues for cache block (sector) copyback operations
— Bus extensions for I/O controller interface operations
— Multiprocessing support features that include the following:
– Hardware enforced, four-state cache coherency protocol (MESI)
– Separate port into cache tags for bus snooping
• In-system testability and debugging features through boundary-scan capability