Features
This section summarizes features of the 604e’s implementation of the PowerPC architecture. Major features
of the 604e are as follows:
• High-performance, superscalar microprocessor
— As many as four instructions can be issued per clock
— As many as seven instructions can start executing per clock (including three integer
instructions)
— Single-clock-cycle execution for most instructions
• Seven independent execution units and two register files
— BPU featuring dynamic branch prediction
– Two-entry reservation station
– Out-of-order execution through two branches
– Shares dispatch bus with CRU
– 64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can
be disabled and invalidated.
– 512-entry branch history table (BHT) with two bits per entry for four levels of prediction—
not-taken, strongly not-taken, taken, strongly taken
— Condition register logical unit
– Two-entry reservation station
– Shares dispatch bus with BPU
— Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU)
– Instructions that execute in the SCIU take one cycle to execute; most instructions that
execute in the MCIU take multiple cycles to execute.
– Each SCIU has a two-entry reservation station to minimize stalls
– The MCIU has a single-entry reservation station and provides early exit (three cycles) for
16- x 32-bit and overflow operations.
– Thirty-two GPRs for integer operands
— Three-stage floating-point unit (FPU)
– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Fully pipelined, single-pass double-precision design
– Hardware support for denormalized numbers
– Two-entry reservation station to minimize stalls
– Thirty-two 64-bit FPRs for single- or double-precision operands
— Load/store unit (LSU)
– Two-entry reservation station to minimize stalls
– Single-cycle, pipelined cache access
– Dedicated adder performs effective address (EA) calculations
– Performs alignment and precision conversion for floating-point data
– Performs alignment and sign extension for integer data
– Four-entry finish load queue (FLQ) provides load miss buffering
– Six-entry store queue
– Supports both big- and little-endian modes
• Rename buffers
— Twelve GPR rename buffers
— Eight FPR rename buffers
— Eight condition register (CR) rename buffers
• Completion unit
— The completion unit retires an instruction from the 16-entry reorder buffer when all instructions
ahead of it have been completed and the instruction has finished execution.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes executed, dispatched, and fetched instructions if branch
is mispredicted
— Retires as many as four instructions per clock
• Separate on-chip instruction and data caches (Harvard architecture)
— 32-Kbyte, four-way set-associative instruction and data caches
— LRU replacement algorithm
— 32-byte (eight-word) cache block size
— Physically indexed/physical tags (Note that the PowerPC architecture refers to physical address
space as real address space.)
— Cache write-back or write-through operation programmable on a per page or per block basis
— Instruction cache can provide four instructions per clock; data cache can provide two words per
clock
— Caches can be disabled in software
— Caches can be locked
— Parity checking performed on both caches
— Data cache coherency (MESI) maintained in hardware
— Secondary data cache support provided
— Instruction cache coherency maintained in software
— Data cache line-fill buffer forwarding. In the 604 only the critical double word of the cache
block was made available to the requesting unit at the time it was burst into the line-fill buffer.
Subsequent data was unavailable until the cache block was filled. On the 604e, subsequent data
is also made available as it arrives in the line-fill buffer.
• Separate memory management units (MMUs) for instructions and data
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— Both TLBs are 128-entry and two-way set associative
— TLBs are hardware reloadable (that is, the page table search is performed in hardware)
— Separate IBATs and DBATs (four each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
— LRU replacement algorithm
— 52-bit virtual address; 32-bit physical address
• Bus interface features
— Selectable processor-to-bus clock frequency ratios of 3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 5:1, and 6:1
— A 64-bit split-transaction external data bus with burst transfers
— Support for address pipelining and limited out-of-order bus transactions
— Four burst write queues—three for cache copyback operations and one for snoop push
operations
— Two single-beat write queues
— Additional signals and signal redefinition for direct-store operations
— Provides a data streaming mode that allows consecutive burst read data transfers to occur
without intervening dead cycles. This mode also disables data retry operations.
— No-DRTRY mode eliminates the DRTRY signal from the qualified bus grant and allows read
operations. This improves performance on read operations for systems that do not use the
DRTRY signal. No-DRTRY mode makes read data available to the processor one bus clock
cycle sooner than if normal mode is used.
• Multiprocessing support features include the following:
— Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are
provided in the instruction cache to indicate only whether a cache block is valid or invalid.
— Separate port into data cache tags for bus snooping
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
• Power management
— DOZE mode suspends instruction execution while allowing cache snooping
— NAP mode suspends all internal clocks except those required for decrementer, time base, and
interrupt logic
— Operating voltage of 2.5

± 0.125 V
• Performance monitor can be used to help in debugging system designs and improving software
efficiency, especially in multiprocessor systems.
• In-system testability and debugging features through JTAG boundary-scan capability