DSP56824 Features
Digital Signal Processing Core
• Efficient 16-bit DSP56800 family DSP engine
• As many as 35 Million Instructions Per Second (MIPS) at 70 MHz
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C Compiler and local variable support
• Software subroutine and interrupt stack with unlimited depth
Memory
• On-chip Harvard architecture permits as many as three simultaneous accesses to program and data
memory
• On-chip memory
— 32 K × 16 Program ROM
— 128 × 16 Program RAM
— 3.5 K × 16 X RAM usable for both data and programs
— 2 K × 16 X data ROM
• Off-chip memory expansion capabilities
— As much as 64 K × 16 X data memory
— As much as 64 K × 16 program memory
— External memory expansion port programmable for 1 to 15 wait states
• Programs can run out of X data RAM
Peripheral Circuits
• External Memory Interface (Port A)
• Sixteen dedicated GPIO pins (eight pins programmable as interrupts)
• Serial Peripheral Interface (SPI) support: Two configurable four-pin ports (SPI0 and SPI1) (or eight
additional GPIO lines)
— Supports LCD drivers, A/D subsystems, and MCU systems
— Supports inter-processor communications in a multiple master system
— Supports demand-driven master or slave devices with high data rates
• Synchronous Serial Interface (SSI) support: One 6-pin port (or six additional GPIO lines)
— Supports serial devices with one or more industry-standard codecs, other DSPs,
microprocessors, and Freescale SPI-compliant peripherals
— Allows implementing synchronous or synchronous transmit and receive sections with separate
or shared internal/external clocks and frame syncs
— Supports Network mode using frame sync and as many as 32 time slots
— Can be configured for 8-bit, 10-bit, 12-bit, and 16-bit data word lengths
• Three programmable 16-bit timers (accessed using two I/O pins that can also be programmed as two
additional GPIO lines)
• Computer-Operating Properly (COP) and Real-Time Interrupt (RTI) timers
• Two external interrupt/mode control pins
• One external reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) 5-pin port for unobtrusive, processor speed-independent
debugging
• Extended debug capability with second breakpoint and 8-level OnCE FIFO history buffer
• Software-programmable, Phase Lock Loop-based (PLL-based) frequency synthesizer for the DSP
core clock
Energy Efficient Design
• A single 2.7–3.6 V power supply
• Power-saving Wait and multiple Stop modes available
• Fully static, HCMOS design for 70 MHz to dc operating frequencies
• Available in plastic 100-pin Thin Quad Flat Pack (TQFP) surface-mount package