[WHITS MICROSELECTRONICS]

FEATURES
■ Access Times of 50, 60, 70, 90, 120 and 150ns
■ 40 pin Ceramic DIP (Package 303)
■ Organized as 128Kx16 and 256Kx16
■ Sector Architecture
    • 8 equal size sectors of 16KBytes each per chip
    • Any combination of sectors can be concurrently erased. Also supports full chip erase
■ 100,000 Erase/Program Cycles Minimum (0°C to 70°C)
■ Data Retention, 10 Years at 125°C
■ Commercial, Industrial and Military Temperature Ranges
■ 5 Volt Programming; 5V ±10% Supply
■ Low Power CMOS
■ Embedded Erase and Program Algorithms
■ TTL Compatible Inputs and CMOS Outputs
■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation
■ Page Program Operation and Internal Program Control Time