1FEATURES
23• 5-Bit LVDS Interface
• No External VCO or Clock Required
• Reclocked Serial Loopthrough With Cable
Driver
• Powerdown Mode
• 3.3V SMBus Configuration Interface
• Small 48-Pin WQFN Package
• Industrial Temperature range: -40°C to +85°C

APPLICATIONS
• SDI Interfaces for:
– Video Cameras
– DVRs
– Video Switchers
– Video Editing Systems

KEY SPECIFICATIONS
• Output compliant with SMPTE 259M-C, SMPTE
292M, SMPTE 424M and DVB-ASI (See Table 1)
• Typical power dissipation: 590 mW
(loopthrough disabled, 3G datarate)
• 0.6 UI Minimum Input Jitter Tolerance

DESCRIPTION
The LMH0341/0041/0071/0051 SDI Deserializers are
part of TI’s family of FPGA-Attach SER/DES products
supporting 5-bit LVDS interfaces with FPGAs. When
paired with a host FPGA the LMH0341 automatically
detects the incoming data rate and decodes the raw
5-bit data words compliant to any of the following
standards: DVB-ASI, SMPTE 259M, SMPTE 292M,
or SMPTE 424M. See Table 1 for details on which
Standards are supported per device.
The interface between the LMH0341 and the host
FPGA consists of a 5-bit wide LVDS bus, an LVDS
clock and an SMBus interface. No external VCOs or
clocks are required. The LMH0341 CDR detects the
frequency from the incoming data stream, generates
a clean clock and transmits both clock and data to
the host FPGA. The LMH0341, LMH0041 and
LMH0071 include a serial reclocked loopthrough with
integrated SMPTE compliant cable driver. Refer to
Table 1 for a complete listing of single channel
deserializers offered in this family.
The FPGA-Attach SER/DES product family is
supported by a suite of IP which allows the design
engineer to quickly develop video applications using
the SER/DES products. The product is packaged in a
physically small 48 pin WQFN package.