1 Features
• Differential line drivers for 30Ω to 55Ω loads and
data rates1 up to 200Mbps, clock frequencies up to
100MHz
• Supports multipoint bus architectures
• Operates from a single 3.3V supply
• Characterized for operation from –40°C to 85°C
• 16-pin SOIC (JEDEC MS-012) and 16-pin TSSOP
(JEDEC MS-153) packaging

2 Applications
• AdvancedTCA™ (ATCA™) Clock Bus Driver
• Clock distribution
• Backplane or cabled multipoint data transmission
in telecommunications, automotive, industrial, and
other computer systems
• Cellular base stations
• Central-office and PBX switching
• Bridges and routers
• Low-power high-speed short-reach alternative to
TIA/EIA-485

3 Description
The SN65MLVD047A is a quadruple line driver that
complies with the TIA/EIA-899 standard, Electrical
Characteristics of Multipoint-Low-Voltage Differential
Signaling (M−LVDS). The output current of this
M−LVDS device has been increased, in comparison
to standard LVDS compliant devices, in order to
support doubly terminated transmission lines and
heavily loaded backplane bus applications. Backplane
applications generally require impedance matching
termination resistors at both ends of the bus. The
effective impedance of a doubly terminated bus can
be as low as 30Ω due to the bus terminations, as
well as the capacitive load of bus interface devices.
SN65MLVD047A drivers allow for operation with loads
as low as 30Ω. The SN65MLVD047A devices allow
for multiple drivers to be present on a single bus.
SN65MLVD047A drivers are high impedance when
disabled or unpowered. Driver edge rate control
is incorporated to support operation. The M−LVDS
standard allows up to 32 nodes (drivers and/or
receivers) to be connected to the same media in a
backplane when multiple bus stubs are expected from
the main transmission line to interface devices. The
SN65MLVD047A provides 9kV ESD protection on all
bus pins.