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CDCLVP111-EP データシート (PDF) - Texas Instruments

CDCLVP111-EP Datasheet PDF - Texas Instruments
部品番号 CDCLVP111-EP
ダウンロード  CDCLVP111-EP ダウンロード
ファイルサイズ   2466.84 Kbytes
ページ   32 Pages
メーカー  TI2 [Texas Instruments]
ホームページ  https://www.ti.com
Logo TI2 - Texas Instruments
部品情報 CDCLVP111-SEP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

CDCLVP111-EP Datasheet (PDF)

Go To PDF Page ダウンロード データシート
CDCLVP111-EP Datasheet PDF - Texas Instruments

部品番号 CDCLVP111-EP
ダウンロード  CDCLVP111-EP Click to download

ファイルサイズ   2466.84 Kbytes
ページ   32 Pages
メーカー  TI2 [Texas Instruments]
ホームページ  https://www.ti.com
Logo TI2 - Texas Instruments
部品情報 CDCLVP111-SEP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

CDCLVP111-EP データシート (HTML) - Texas Instruments


CDCLVP111-EP 製品詳細

1 Features
• Vendor item drawing (VID#): V62/12624-02YE
• Radiation tolerance:
– Total ionizing dose (TID): 50krad
– Single-event latch-up (SEL): 43MeV × cm2/mg
• Junction temperature range: –55°C to 125°C
• Distributes One Differential Clock Input Pair
(LVDS, CML, SSTL, LVPECL, LVECL) to 10
Differential LVPECL or LVECL outputs
• Supports a Wide Supply Voltage Range From
2.375V to 3.8V
• Selectable Clock Input Through CLK_SEL
• Low-Output Skew (Typical 15ps) for Clock-
Distribution Applications
– Additive Jitter Less Than 1ps
– Propagation Delay Less Than 355ps
– Open Input Default State
– LVDS, CML, SSTL Input Compatible
• VBB Reference Voltage Output for Single-Ended
Clocking
• Frequency Range From DC to 3.5GHz
• Space-enhanced plastic (space EP):
– SUPPORTS DEFENSE, AND AEROSPACE
APPLICATIONS
– Controlled baseline
– One assembly and test Site
– One fabrication site
– Extended product life cycle
– Product traceability
– Outgassing test performed per ASTM E595

2 Applications
• Designed for Driving 50Ω Transmission Lines
• High-Performance Clock Distribution
• Communications payloads
• Radar imaging payload
• Command data handling

3 Description
The CDCLVP111-SEP clock driver distributes one
differential clock pair of LVPECL input, (CLK0, CLK1)
to ten pairs of differential LVPECL clock (Q0, Q9)
outputs with minimum skew for clock distribution.
The CDCLVP111-SEP can accept two clock sources
into an input multiplexer. The CDCLVP111-SEP is
specifically designed for driving 50Ω transmission
lines. When an output pin is not used, leaving the pin
open is recommended to reduce power consumption.
If only one of the output pins from a differential
pair is used, the other output pin must be identically
terminated to 50Ω.
The VBB reference voltage output is used if singleended
input operation is required. In this case, the
VBB pin must be connected to CLK0 and bypassed to
GND using a 10nF capacitor.
For high-speed performance, the differential mode is
strongly recommended.
The CDCLVP111-SEP is characterized for operation
from –55°C to 125°C.




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