1 Features
• Low-Voltage Differential 30Ω to 55Ω Line Drivers
and Receivers for Signaling Rates(1) Up to
250Mbps; Clock Frequencies Up to
125MHz
• Meets or Exceeds the M-LVDS Standard TIA/
EIA-899 for Multipoint Data Interchange
• Controlled Driver Output Voltage Transition Times
for Improved Signal Quality
• –1V to 3.4V Common-Mode Voltage Range Allows
Data Transfer With 2V of Ground Noise
• Bus Pins High Impedance When Driver Disabled
or VCC ≤ 1.5V
• Independent Enables for each Driver and Receiver
• Enhanced ESD Protection: 7kV HBM on all Pins
• 48 pin 7 X 7 QFN (RGZ)
• M-LVDS Bus Power Up/Down Glitch Free

2 Applications
• Parallel Multipoint Data and Clock
Transmission Via Backplanes and Cables
• Low-Power High-Speed Short-Reach Alternative to
TIA/EIA-485
• Cellular Base Stations
• Central-Office Switches
• Network Switches and Routers

3 Description
The SN65MLVD040 provides four half-duplex
transceivers for transmitting and receiving Multipoint-
Low-Voltage Differential Signals in full compliance
with the TIA/EIA-899 (M-LVDS) standard, which
are optimized to operate at signaling rates up to
250Mbps. The driver outputs have been designed to
support multipoint buses presenting loads as low as
30Ω and incorporates controlled transition times to
allow for stubs off of the backplane transmission line.
The M-LVDS standard defines two types of receivers,
designated as Type-1 and Type-2. Type-1 receivers
have thresholds centered about zero with 25mV of
hysteresis to prevent output oscillations with loss
of input; Type-2 receivers implement a failsafe by
using an offset threshold. The xFSEN pins is used
to select the Type-1 and Type-2 receiver for each
of the channels. In addition, the driver rise and fall
times are between 1ns and 2ns, complying with the
M-LVDS standard to provide operation at 250Mbps
while also accommodating stubs on the bus. Receiver
outputs are slew rate controlled to reduce EMI and
crosstalk effects associated with large current surges.
The M-LVDS standard allows for 32 nodes on the bus
providing a high-speed replacement for RS-485 where
lower common-mode can be tolerated or when higher
signaling rates are needed.
The driver logic inputs and the receiver logic outputs
are on separate pins rather than tied together as in
some transceiver designs. The drivers have separate
enables (DE) and so does the receivers ( RE). This
arrangement of separate logic inputs, logic outputs,
and enable pins allows for a listen-while-talking
operation. The devices are characterized for operation
from –40°C to 85°C.