1 Features
• Low-voltage differential 30Ω to 55Ω line receivers
for signaling rates1 up to 250Mbps; Clock
Frequencies up to 125MHz
• Type-1 receiver incorporates 25mV of input
threshold hysteresis
• Type-2 receiver provides 100mV offset threshold to
detect open-circuit and idle-bus conditions
• Wide receiver input common-mode voltage range,
–1V to 3.4V, allows 2V of ground noise
• Meets or exceeds the M-LVDS standard TIA/
EIA-899 for multipoint topology
• High input impedance when Vcc ≤ 1.5V
• Enhanced ESD Protection: 7kV HBM on all pins
• 48-Pin 7 X 7 QFN (RGZ)

2 Applications
• Parallel multipoint data and clock transmission via
backplanes and cables
• Cellular base stations
• Central office switches
• Network switches and routers

3 Description
The SN65MLVD048 is a quad-channel M-LVDS
receiver. This device is designed in full compliance
with the TIA/EIA-899 (M-LVDS) standard, which
is optimized to operate at signaling rates up to
250Mbps. Each receiver channel is controlled by
a receive enable ( RE). When RE = low, the
corresponding channel is enabled; when RE = high,
the corresponding channel is disabled.
The M-LVDS standard defines two types of receivers,
designated as Type-1 and Type-2. Type-1 receivers
have thresholds centered about zero with 25mV of
hysteresis to prevent output oscillations with loss
of input; Type-2 receivers implement a failsafe by
using an offset threshold. Receiver outputs are slew
rate controlled to reduce EMI and crosstalk effects
associated with large current surges.
The devices are characterized for operation from –
40°C to 85°C.