DESCRIPTION
The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table regardless of the level at the other inputs.
A High level on the clock (CP) input enables the J and K inputs and data will be accepted. The logic levels and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CP.