▪ High-performance radio clock synchronizer clock
— Device clock domain (RF-PLL) with support for JESD204B/C
— Digital clock domain (Ethernet, FEC) with support for eEEC
and T-BC/T-TSC Class C
▪ 2 differential clock reference inputs
— 1PPS (1Hz) to 1GHz input frequency
▪ Dual DPLL front-end with independent clock paths
— External control of the DCO for IEEE1588
— Digital holdover with a 1.1 × 10-7 ppb accuracy
— Programmable DPLL loop bandwidth 1mHz – 6kHz
— Configurable phase delay (range: 1UI)
— Hitless input switching with < 1ns output phase error
▪ Reference monitors for input LOS, activity and frequency
▪ 1 external synchronization input for JESD204B/C (LVCMOS)
▪ 16 differential outputs
▪ Dedicated phase management capabilities
▪ Optimized for low phase noise:
— Device clocks: -149.9dBc/Hz (1MHz offset; 245.76MHz clock)
▪ Supply voltage (core): 3.3V; (outputs): 3.3V, 2.5V, and 1.8V
▪ Package: 10 × 10 mm 88-VFQFPN
▪ Board temperature range: -40°C to +105°C