▪ Flexible 1.8V, 2.5V, or 3.3V power-rails
▪ High-performance, low phase noise PLL, < 0.5ps
RMS typical phase jitter on outputs
▪ Four banks of internal OTP memory
• In-system or factory programmable
• Two select pins accessible with processor
GPIOs or bootstrapping
▪ I2C serial programming interface
• 0xD0 or 0xD4 I2C address options allows
multiple devices configured in a same system
▪ LVCMOS reference clock output
▪ Four universal output pairs individually configurable:
• Differential (LVPECL, LVDS or HCSL)
• Two LVCMOS in-phase or 180 degrees out of phase
• I/O VDDs can be mixed and matched,
supporting 1.8V (LVDS and LVCMOS), 2.5V, or 3.3V
▪ Output frequency ranges:
• Single-ended clock outputs: 1MHz to 200MHz
• Differential clock outputs: 1MHz to 350MHz
▪ Redundant clock input with manual switchover
▪ Programmable output enable or power-down mode
▪ 4.0 × 4.0 mm 24-VFQFPN wettable flank package