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74HC08D-Q100 データシート (PDF) - Nexperia B.V. All rights reserved

74HC08D-Q100 Datasheet PDF - Nexperia B.V. All rights reserved
部品番号 74HC08D-Q100
ダウンロード  74HC08D-Q100 ダウンロード
ファイルサイズ   200.15 Kbytes
ページ   18 Pages
メーカー  NEXPERIA [Nexperia B.V. All rights reserved]
ホームページ  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
部品情報 Quad 2-input multiplexer

74HC08D-Q100 Datasheet (PDF)

Go To PDF Page ダウンロード データシート
74HC08D-Q100 Datasheet PDF - Nexperia B.V. All rights reserved

部品番号 74HC08D-Q100
ダウンロード  74HC08D-Q100 Click to download

ファイルサイズ   200.15 Kbytes
ページ   18 Pages
メーカー  NEXPERIA [Nexperia B.V. All rights reserved]
ホームページ  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
部品情報 Quad 2-input multiplexer

74HC08D-Q100 データシート (HTML) - Nexperia B.V. All rights reserved


74HC08D-Q100 製品詳細

General description
The 74HC157; 74HCT157 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT157 are quad 2-input multiplexers which select 4 bits of data from two
sources under the control of a common data select input (S). The enable input (E) is
active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of
all other input conditions.
Moving the data from two groups of registers to four common output buses is a common
use of the 74HC/HCT157. The state of the common data select input (S) determines the
particular register from which the data comes. It can also be used as function generator.
The device is useful for implementing highly irregular logic by generating any four of the
16 different functions of two variables with one variable common. The 74HC/HCT157 is
logic implementation of a 4-pole, 2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations are:
1Y = E (1I1 S + 1I0 S)
2Y = E (2I1 S + 2I0 S)
3Y = E (3I1 S + 3I0 S)
4Y = E (4I1 S + 4I0 S)
The 74HC/HCT157 is identical to the 74HC158 but has non-inverting (true) outputs.
Features and benefits
 Low-power dissipation
 Complies with JEDEC standard no. 7A
 Input levels:
 For 74HC157: CMOS level
 For 74HCT157: TTL level
 Non-inverting data path
 ESD protection:
 HBM JESD22-A114F exceeds 2 000 V
 MM JESD22-A115-A exceeds 200 V
 Specified from 40 C to +85 C and from 40 C to +125 C




同様の部品番号 - 74HC08D-Q100

メーカー部品番号データシート部品情報
logo
Nexperia B.V. All right...
74HC08D-Q100 NEXPERIA-74HC08D-Q100 Datasheet
207Kb / 15P
Quad 2-input AND gate
74HC08D-Q100 NEXPERIA-74HC08D-Q100 Datasheet
135Kb / 14P
Quad 2-input AND gate
Rev. 1 16 July 2012
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同様の説明 - 74HC08D-Q100

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