Description
The V58C265404S is a four bank DDR DRAM organized as 4 banks x 4Mbit x 4. The V58C265404S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock

Features
■ 4 banks x 4Mbit x 4 organization
■ High speed data transfer rates with system  frequency up to 166 MHz ■ Data Mask for Write Control (DM)
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 2.5, 3
■ Programmable Wrap Sequence: Sequential  or Interleave
■ Programmable Burst Length:
   2, 4, 8 for Sequential Type
   2, 4, 8 for Interleave Type
■ Automatic and Controlled Precharge Command
■ Suspend Mode and Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 66-pin 400 mil TSOP-II
■ SSTL-2 Compatible I/Os
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQs) for input and  output data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with  CLK transitions
■ Differential clock inputs CLK and CLK
■ Power supply 2.5V ± 0.2V