Description
The V62C318256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and three state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

Features
■ High-speed: 35, 70 ns
■ Ultra low DC operating current of 2mA (max.)
■ Low Power Dissipation:
   – TTL Standby: 0.5 mA (Max.)
   – CMOS Standby: 10 µA (Max.)
■ Fully static operation
■ All inputs and outputs directly compatible
■ Three state outputs
■ Ultra low data retention current (VCC = 2V)
■ Extended operating voltage: 2.7V–3.6V
■ Packages
   – 28-pin TSOP (Standard)
   – 28-pin 300 mil SOP (450 mil pin-to-pin)