GENERAL DESCRIPTION

The W641GG2JB 1-Gbit GDDR3 GRAPHICS SDRAM is a high speed dynamic random-access memory designed for applications requiring high bandwidth. It contains 1,073,741,824 bits. The device can be configured to operate in two different modes:

• in 2-CS mode the chip is organized as two 512 Mbit memories of 8 banks each, with 4096 row locations and 512 column locations per bank.

• in 1-CS mode the chip is organized as one 1 Gbit memory, with 8192 row locations and 512 column locations perbank.

The GDDR3 GRAPHICS SDRAM uses a double data rate architecture to achieve high speed operation. The double

data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the GDDR3 GRAPHICS SDRAM effectively consists of a 4n data transfer every two clock cycles at the internal DRAM core and four corresponding n-bit wide, one-half-clock cycle data transfers at the I/O pins.

FEATURES

• Density: 1Gbit

• Power supply (VDD, VDDQ): 1.8V 0.1V

• Organization: 1 Chip Select x 8 banks x 4M words x 32 bits (1-CS mode) and 2 Chip Select x 8 banks x 2M words x 32 bits (2-CS mode)

• Eight internal banks per Chip Select for concurrent operation

• 4n prefetch architecture: 128 bit per array Read or Write access

• Double-data rate architecture: two data transfers per clock cycle

• Single ended interface for data, address and command

• Differential clock inputs CLK, CLK#

• Commands entered on each positive CLK edge

• Single ended Read strobe (RDQS) per byte, edge-aligned with Read data

• Single ended Write strobe (WDQS) per byte, center aligned with Write data

• Write data mask (DM) function

• DLL aligns DQ and RDQS transitions with CLK clock edges for Reads

• Burst length (BL): 4 or 8

• Sequential burst type only

• Programmable CAS latency: 7 to 14

• Programmable Write latency: 3 to 7

• Auto precharge option for each burst access

• Pseudo open drain outputs with 40 pulldown, 40 pullup

• ODT: nom. values of 60 , 120 or 240

• Programmable termination and driver strength offsets

• Refresh cycles: 8192 cycles/32ms

• Auto-refresh and self-refresh modes

• ODT and output drive strength auto-calibration with external resistor ZQ pin (240 )

• Programmable IO interface including on chip termination (ODT)

• tRAS lockout support

• Vendor ID for device identification

• Mirror function with MF pin

• Boundary Scan function with SEN pin

• tWR programmable for Writes with Auto-Precharge

• Calibrated output drive. Active termination support

• Short RAS to CAS timing for Writes

• Operating case temperature range: Tcase = 0°C to +105°C

• Package: 136-ball TFBGA.

• RoHS Compliant Product