PRODUCT DESCRIPTION
The SST39LF200A/400A/800A and SST39VF200A/400A/800A devices are 128K x16 / 256K x16 / 512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF200A/400A/800A write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF200A/400A/800A write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories.

FEATURES:
• Organized as 128K x16 / 256K x16 / 512K x16
• Single Voltage Read and Write Operations
   – 3.0-3.6V for SST39LF200A/400A/800A
   – 2.7-3.6V for SST39VF200A/400A/800A
• Superior Reliability
   – Endurance: 100,000 Cycles (typical)
   – Greater than 100 years Data Retention
• Low Power Consumption (typical values at 14 MHz)
   – Active Current: 9 mA (typical)
   – Standby Current: 3 µA (typical)
• Sector-Erase Capability
   – Uniform 2 KWord sectors
• Block-Erase Capability
   – Uniform 32 KWord blocks
• Fast Read Access Time
   – 55 ns for SST39LF200A/400A/800A
   – 70 ns for SST39VF200A/400A/800A
• Latched Address and Data
• Fast Erase and Word-Program
   – Sector-Erase Time: 18 ms (typical)
   – Block-Erase Time: 18 ms (typical)
   – Chip-Erase Time: 70 ms (typical)
   – Word-Program Time: 14 µs (typical)
   – Chip Rewrite Time:
      2 seconds (typical) for SST39LF/VF200A
      4 seconds (typical) for SST39LF/VF400A
      8 seconds (typical) for SST39LF/VF800A
• Automatic Write Timing
   – Internal VPP Generation
• End-of-Write Detection
   – Toggle Bit
   – Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
   – Flash EEPROM Pinouts and command sets
• Packages Available
   – 48-lead TSOP (12mm x 20mm)
   – 48-ball TFBGA (6mm x 8mm)
   – 48-ball WFBGA (4mm x 6mm)
   – 48-bump XFLGA (4mm x 6mm) – 4 and 8Mbit
• All non-Pb (lead-free) devices are RoHS compliant