Application Note
High speed microprocessors line Intels Pentium/P6®, Apple PowerPC®, SPARC® and other CISC and RISC based systems need well-controlled and precise clock signals to maintain a synchronous systems. The fast edge rated clock signals will exhibit transmission line effects on the clock lines resulting in undershoots and overshoots. The integrated PECL termination is designed to suppress the undershoots and overshoots on the clock lines. The PECL RC terminator dissipates very low power compared to the resistor termination network.

Features
• Stable resistor network
• Reduces power dissipation on the clock lines
• Ideal for high-speed clock termination
• Reduces board space by 70% vs. 1206 discretes and component count by more than 50%

Applications
• PECL clock termination