Functional Description
I/O Pin Operation
Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts as a logic input, allowing the determination of assigned device functions. A short time after power-up, the logic state of the pin is latched and the pin becomes a clock output. This feature reduces device pin count by combining clock outputs with input select pins.

Features
• Maximized EMI suppression using Cypress’s Spread Spectrum Technology
• Reduces measured EMI by as much as 10 dB
• I2C programmable to 133 MHz
• Two skew-controlled copies of CPU output
• SEL100/66# selects CPU frequency (100 or 66.8 MHz)
• Seven copies of PCI output (synchronous w/CPU output)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz clock is determined by resistor straps on power-up
• One high-drive output buffer that produces a copy of the 14.318-MHz reference
• Isolated core VDD pin for noise reduction