Overview
The EM658160 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 64 Mbits. It is internally configured as a quad 1M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and /CK. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM658160 provides programmable Read or Write burst lengths of 2, 4, 8, full page.

Features
• Fast clock rate: 300/285/250/200/166/143/125MHz
• Differential Clock CK & /CK
• Bi-directional DQS
• DLL enable/disable by EMRS
• Fully synchronous operation
• Internal pipeline architecture
• Four internal banks, 1M x 16-bit for each bank
• Programmable Mode and Extended Mode registers
    - /CAS Latency: 2, 2.5, 3
    - Burst length: 2, 4, 8
    - Burst Type: Sequential & Interleaved
• Individual byte write mask control
• DM Write Latency = 0
• Auto Refresh and Self Refresh
• 4096 refresh cycles / 64ms
• Precharge & active power down
• Power supplies: VDD = 3.3V ± 0.3V
                             VDDQ = 2.5V ± 0.2V
• Interface: SSTL_2 I/O Interface
• Package: 66 Pin TSOP II, 0.65mm pin pitch