The 82434LX/82434NX PCI, Cache, Memory Controllers (PCMC) integrate the cache and main memory DRAM control functions and provide bus control for transfers between the CPU, cache, main memory, and the PCI Local Bus. The cache controller supports write-back (or write-through for 82434LX) cache policy and cache sizes of 256-KBytes and 512-KBytes. The cache memory can be implemented with either standard or burst SRAMs. The PCMC cache controller integrates a high-performance Tag RAM to reduce system cost.

■ Supports the PentiumTM Processor at iCOMPTM Index 510T60 MHz and iCOMP Index 567T66 MHz
■ Supports the Pentium Processor at iCOMP Index 735T90 MHz, iCOMP Index 815T100 MHz, and iCOMP Index 610T75 MHz
■ Supports Pipelined Addressing Capability of the Pentium Processor
■ The 82430NX Drives 3.3V Signal Levels on the CPU and Cache Interfaces
■ High Performance CPU/PCI/Memory Interfaces via Posted Write and Read Prefetch Buffers
■ Fully Synchronous PCI Interface with Full Bus Master Capability
■ Supports the Pentium Processor Internal Cache in Either Write-Through or Write-Back Mode
■ Programmable Attribute Map of DOS and BIOS Regions for System Flexibility
■ Integrated Low Skew Clock Driver for Distributing Host Clock
■ Integrated Second Level Cache Controller
    — Integrated Cache Tag RAM
    — Write-Through and Write-Back Cache Modes for the 82434LX
    — Write-Back for the 82434NX
    — 82434NX Supports Low-Power Cache Standby
    — Direct Mapped Organization
    — Supports Standard and Burst SRAMs
    — 256-KByte and 512-KByte Sizes
    — Cache Hit Cycle of 3-1-1-1 on Reads and Writes Using Burst SRAMs
    — Cache Hit Cycle of 3-2-2-2 on Reads and 4-2-2-2 on Writes Using Standard SRAMs
■ Integrated DRAM Controller
    — Supports 2 MBytes to 192 MBytes of Cacheable Main Memory for the 82434LX
    — Supports 2 MBytes to 512 MBytes of Cacheable Main Memory for the 82434NX
    — Supports DRAM Access Times of 70 ns and 60 ns
    — CPU Writes Posted to DRAM 4-1-1-1
    — Refresh Cycles Decoupled from ISA Refresh to Reduce the DRAM Access Latency
    — Six RASÝ Lines (82434LX)
    — Eight RASÝ Lines (82434NX)
    — Refresh by RASÝ-Only, or CASBefore-RASÝ, in Single or Burst of Four
■ Host/PCI Bridge
    — Translates CPU Cycles into PCI Bus Cycles
    — Translates Back-to-Back Sequential CPU Memory Writes into PCI Burst Cycles
    — Burst Mode Writes to PCI in Zero PCI Wait-States (i.e. Data Transfer Every Cycle)
    — Full Concurrency Between CPU-toMain Memory and PCI-to-PCI Transactions
    — Full Concurrency Between CPU-toSecond Level Cache and PCI-to-Main Memory Transactions
    — Same Cache and Memory System Logic Design for ISA and EISA Systems
    — Cache Snoop Filter Ensures Data Consistency for PCI-to-Main Memory Transactions
■ 208-Pin QFP Package