AD7721

REV. A

–12–

PARALLEL INTERFACE

Read Operation

The device defaults to parallel mode if

CS, RD and WR are not

tied to DGND together. Figure 11 shows a timing diagram for

reading from the AD7721 in the parallel mode. When operating

the device in parallel mode,

CS and RD should be tied to

DGND permanently except when control information is being

written to the AD7721.

DRDY goes high for 2 clock cycles to

indicate that new data is available from the interface. The

AD7721 outputs this data after the falling edge of

DRDY. This

DRDY pin can be used to drive an edge-triggered interrupt of a

microprocessor.

Write Operation

The write operation is used to write data into the control regis-

ter. The outputs of the control register select the analog input

range, allow the part to be put into power-down (standby)

mode, define the function of the DVAL/

SYNC pin, and initiate

the calibration routine. After power-up and after at least 16

clock cycles, the control register must be written to. A cali-

bration must also be performed at least once after power-up to

set the calibration registers. The function of each bit in the

control register is shown in Table I. When writing to the con-

trol register, the

RD pin must be taken high so that the pins D0

to D11 are configured as inputs.

DATA OUT (O)

SCLK (O)

DB0

DB10

DB11

DB12

DB13

DB14

DB15

RFS (I) / DRDY (O)

NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.

t

9

Figure 10. Serial Mode Output Register Read

DRDY (O)

DB0–DB11 (O)

RD (I)

CS (I)

NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.

Figure 11. Parallel Mode Output Register Read

NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.

WR (I)

VALID DATA

CS (I)

DB0–DB11 (I)

Figure 12. Write Timing Diagram