データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

CS53L32A-BZ データシート(PDF) 21 Page - Cirrus Logic

部品番号 CS53L32A-BZ
部品情報  Low Voltage, Stereo A/D Converter
PDF  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS53L32A-BZ データシート(HTML) 21 Page - Cirrus Logic

Back Button CS53L32A-BZ Datasheet HTML 17Page - Cirrus Logic CS53L32A-BZ Datasheet HTML 18Page - Cirrus Logic CS53L32A-BZ Datasheet HTML 19Page - Cirrus Logic CS53L32A-BZ Datasheet HTML 20Page - Cirrus Logic CS53L32A-BZ Datasheet HTML 21Page - Cirrus Logic CS53L32A-BZ Datasheet HTML 22Page - Cirrus Logic CS53L32A-BZ Datasheet HTML 23Page - Cirrus Logic CS53L32A-BZ Datasheet HTML 24Page - Cirrus Logic CS53L32A-BZ Datasheet HTML 25Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 40 page
background image
CS53L32A
DS513F1
21
4.7
MASTER MODE
Interface Control Register (address 02h)
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Slave Mode
Function:
Configures the device for master or slave operation when in Control Port mode.
4.8
DIGITAL INTERFACE FORMAT
Interface Control Register (address 02h)
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Format 0 (I2S, up to 24-bit data, Data valid on positive edge of SCLK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 18 through 21.
76543
210
RESERVED
MCLKDIV
RATIO1
RATIO0
MASTER
DIF2
DIF1
DIF0
MASTER
MODE
0
Slave Mode
1
Master Mode
Table 6. Master/Slave Mode Selection
7654
3
210
RESERVED
MCLKDIV
RATIO1
RATIO0
MASTER
DIF2
DIF1
DIF0
DIF2 DIF1 DIF0
DESCRIPTION
Format
FIGURE
00
0
I2S, up to 24-bit Data, Data valid on positive edge of SCLK
018
0
0
1
Left Justified, up to 24-bit Data, Data valid on positive edge of SCLK
1
19
0
1
0
Reserved
2
-
0
1
1
Right Justified, 16-bit Data, Data valid on positive edge of SCLK
3
18
1
0
0
Right Justified, 24-bit Data, Data valid on positive edge of SCLK
4
19
1
0
1
Right Justified, 18-bit Data, Data valid on positive edge of SCLK
5
20
1
1
0
Right Justified, 20-bit Data, Data valid on positive edge of SCLK
6
21
1
1
1
Reserved
7
-
Table 7. Digital Interface Format



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com