IIS2DH datasheet(13/49 Pages) STMICROELECTRONICS

部品番号	IIS2DH

部品情報	Ultra-low-power high-performance 3-axis accelerometer with digital output for industrial applications

PDF	49 Pages

Scroll/Zoom	100%

メーカー	STMICROELECTRONICS [STMicroelectronics]

ホームページ	http://www.st.com

Logo

13 / 49 page

DocID027668 Rev 2

13/49

IIS2DH

Mechanical and electrical specifications

2.4

Communication interface characteristics

2.4.1

SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Figure 3. SPI slave timing diagram

1. When no communication is ongoing, data on SDO is driven by internal pull-up resistors.

Note:

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output

ports.

Table 6. SPI slave timing values

Symbol

Parameter

Value (1)

Unit

Min

Max

tc(SPC)

SPI clock cycle

100

fc(SPC)

SPI clock frequency

MHz

tsu(CS)

CS setup time

th(CS)

CS hold time

tsu(SI)

SDI input setup time

th(SI)

SDI input hold time

tv(SO)

SDO valid output time

th(SO)

SDO output hold time

tdis(SO)

SDO output disable time

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not

tested in production.

IIS2DH データシート(PDF) 13 Page - STMicroelectronics

IIS2DH データシート(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

データシートダウンロード